make is automatically attempting to link even when I pass -c in my makefile -

i'm new makefiles, apologize in advance if silly question. removed variables makefile because weren't working (gnu make tells me $(myvar) should replaces value of myvar, output of make showing me not happening), apologize ugliness , more 80 character lines.

acolibobj = acolibinit acoglobaldefs acolibinterface: $(acolibobj).o acolibinit.o:     gcc -fpic -g -c -wall -i/usr/include/dc1394 -o acolibinit.o acocommands/acolibinterface/acolibinit.c acoglobaldefs.o:     gcc -fpic -g -c -wall -i/usr/include/dc1394 -o acoglobaldefs.o acocommands/acolibinterface/acoglobaldefs.c 

when run makefile get:

gcc -fpic -g -c -wall -i/usr/include/dc1394 -o acolibinit.o acocommands/acolibinterface/acolibinit.c cc   acolibinit.o   -o acolibinit gcc: acolibinit.o: no such file or directory gcc: no input files make: *** [acolibinit] error 1 

so far can tell, what's happening make trying compile , link, though explicitly added -c flag. when run "gcc -fpic -g -c..." myself (from bash), not problems @ all. why make go on try "cc acolibinit.o -o acolibinit"?

make trying build acolibinit. has built-in rule specifies "whatever" can produced linking "whatever.o", why cc line.

this line:

acolibinterface: $(acolibobj).o 

expands to:

acolibinterface: acolibinit acoglobaldefs.o 

(note absence of .o on first dependency). why it's trying link acolibinit.

try this:

acolibinterface: $(addsuffix .o,$(acolibobj)) 

if want .o files dependencies target.